1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device fabricated with a chip design for preventing an inner lead from contacting an edge and a metal interconnection of a semiconductor chip of a tape carrier package (TCP) which is one type of semiconductor packages.
2. Description of Related Arts
A tape carrier package is one type of conventional semiconductor device. In the semiconductor device of this type, as shown in FIG. 5, an external interconnection (inner lead) 11 is bonded to a bump 9 which is formed on a surface of a semiconductor chip 1a having various devices and circuits with intervention of a pad (not shown).
To fabricate the semiconductor package with the aforesaid construction, the semiconductor chip 1a having the bump 9 is set on a bonding stage 16. In turn, the bump 9 is positioned in alignment with the inner lead 11 extending from a device hole for mounting a chip of a tape carrier 15. Thereafter, the inner lead 11 and the bump 9 are heated and pressed by means of a bonding tool 14 for eutectic bonding therebetween. The bump 9 and the inner lead 11 are generally plated with gold and tin, respectively, and therefore the bonding between the bump 9 and the inner lead 11 is achieved by forming a eutectic alloy of gold and tin therebetween.
The pad of the semiconductor chip is generally formed in a peripheral region of the chip. In some cases, a metal interconnection such as a power supply line is provided between the pad and an edge of the chip because of restriction on circuit arrangement. As shown in FIGS. 6 and 7, an insulation film 5 is formed in a device formation region on an active region and a field oxide film 2 which is formed on a region other than the active region of a semiconductor substrate 1, and the metal interconnection 17 is formed on this insulation film 5. The inner lead 11 crosses the metal interconnection 17 as shown in FIG. 6. The semiconductor substrate 1 is exposed along an edge 12 of the semiconductor chip 1a, because boundaries of a plurality of chips formed on a wafer are defined by scribed lines for dieing the chips out of the wafer.
When the inner lead 11 is bonded to the semiconductor chip 1a at bump 9 on pad 13, heat of the bonding tool 14 is conducted to the inner lead 11, thereby causing the inner lead 11 to sag down due to thermal expansion thereof. Further, the eutectic alloy formed between the bump 9 and inner lead 11 and tin of the tin-plated inner lead 11 are melted by the heat of the bonding tool 14 and sag on the semiconductor chip to pressure it or cause the positional offset of the bonding tool 14. This deteriorates the aforesaid problem. In the worst case, a crack occurs in an insulation film 10 formed on the metal interconnection 17, resulting in a short circuit between the metal interconnection 17 and the inner lead 11 or between the inner lead 11 and the edge 12 of the semiconductor chip 1 or in the corrosion of the metal interconnection 17 due to moisture penetrating from the crack.
There has been proposed a method for forming a metal interconnection in an indentation such as formed between dummy electrodes to prevent the metal interconnection from being slidingly offset when a lateral stress is applied to the semiconductor chip. However, no consideration is given to the aforesaid problem concerning the bonding of the inner lead. The dummy electrodes are useless to prevent the inner lead from sagging due to heat or from being short-circuited to the edge of the semiconductor chip. Further, there is a possibility that a plurality of inner leads are short-circuited to one dummy electrode since the inner leads cross the dummy electrode extending parallel to the metal interconnection. In such an event, an unintended signal is applied to the pad via the dummy electrode, resulting in an erroneous operation of the semiconductor device.